Vi prøver noget nyt med 3 faste priser på timing analyse til FPGA baserede designs:
- Simpelt design – DKK 15.000
- Standard design – DKK 45.000
- Komplekst design – DKK 145.000
Vi syntes der skal være plads til historier, cases, teknologi og debat. Du er velkommen til at kommentere på alt her - vi velkommer dialogen.
Vi omfavner gerne globaliseringstanker, men holder fast i at vi som udviklere har stor fordel af det, vi lærer ved at arbejde med dygtige lokale montagevirksomheder til produktion af elektronik prototyper. Derfor lader vi nu for andet år vores læsere kåre den bedste danske prototype montagevirksomhed.
Denne gang er det en opgave som er nem at beskrive. Som med mange af vores brainere er det også en type løsning som er oplagt og nem når man kender svaret.
If you read about Scrum from the software world, you learn how important it is to make the sprint demo as close as possible to the real product in a realistic user scenario. Some obsess over it to a point, where this becomes a problem for adapting Scrum to hardware development. I want to change that – a demo need NOT be the working product, in order to be valuable and useful.
This post previously appeared on the AgileSOC blog by @nosnhojn – so please go there to join the discussions.
Ugens feel-good historie var den om 13-Ã¥rige Aidan, som havde opfundet en ny mÃ¥de at placere solceller pÃ¥, sÃ¥ de sad lige som bladene pÃ¥ et træ – optimeret af naturen. Den historie gik verden rundt, og var da ogsÃ¥ rigtig sød. Gravede man et spadestik dybere, var der mange gode grunde til, at det ikke rigtig var en god idé, og de pÃ¥stÃ¥ede 20% forbedring var mÃ¥lt forkert.
Agile methods for hardware development is gaining momentum – both Scrum and other techniques are becoming more common.
So what are the best resources and people to learn more about agile hardware development from?
The question was recently raised by @larsthorup of Zealake, sparked by a question from his talk on Elephant Carpaccio (dividing big tasks into thin slices).
I am not sure I know the right answer, but here is a list of the top 8 resources I can think of right now.
Please help me expand the list with your best links and input. Læs resten »
A generally accepted method for validating Power Distribution Networks (PDN’s) – bypass capacitors on Printed Circuit Boards (PCB) by sweeping for |Z| vs. f – have been established as a best practice. This is being discussed at conferences like DesignCon in Silicon Valley.
We did a quick video introduction on how to check your timing constraints in Altera.
To achieve a good quality of a FPGA design – you need a good architecture, good RTL, pin-out files, and a flow and tool than can handle synthesis, place and route, bit file generation etc. One part of the design that in many cases is considered less important is timing constraining and timing analysis.