We did a quick video introduction on how to check your timing constraints in Altera.
Tag ‘constraints’
Quick FPGA Timing Analysis Check
tors jul 14, 2011
To achieve a good quality of a FPGA design – you need a good architecture, good RTL, pin-out files, and a flow and tool than can handle synthesis, place and route, bit file generation etc. One part of the design that in many cases is considered less important is timing constraining and timing analysis.