Quick FPGA Timing Analysis Check

tors jul 14, 2011 (Anders Enggaard)

To achieve a good quality of a FPGA design – you need a good architecture, good RTL, pin-out files, and a flow and tool than can handle synthesis, place and route, bit file generation etc. One part of the design that in many cases is considered less important is timing constraining and timing analysis.

Why? – I don’t know.

I consider both timing constraining and analysis very important and the tasks are rightfully to be considered equally important as doing solid VHDL coding. Reason – well – the brilliant functions built into the FPGA will be of no use at all if the FPGA is not able to communicate with the circuitry surrounding the FPGA.

Luck or engineering?

If your design doesn’t include timing constraining you may experience that your design is working anyway – but in my eyes this as based on luck rather than good engineering. The issue is that you do not have a proof that your IO interfaces will meet the timing requirements of the devices attached to your FPGA or if the registers inside your FPGA obey the rules of setup and hold.

If you want certainty you will need to do design timing constraining. And yes – this is actually a design task that requires information about your PCB in terms of signal flight and settling times, timing data from the devices attached to your FPGA, etc. After the design constraining you will subsequently need to examine the actual timing performance achieved by execution of your timing analysis.

The timing constraints are typically added to your design by use of ASCII type constraint files .ucf files for Xilinx FPGAs and .sdc files for Altera FPGAs. In these files you specify the clocks in the system (frequency/phase/jitter/etc) , the input timing (setup/hold) , the output timing (clock to output min/max), delays through combinatorial paths, and some more advanced stuff.



In case you are in doubt if your FPGA design includes timing constraints it is quite easy to determine – see the short video. Using Altera as the example here. There is another video on Xilinx Timing Analysis available as well.

Q: What are the minimum set of timing constraints you think you can get away with?

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